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| single-chip 32-bit cmos microcomputer features ? cpu .......................................................... m32r family cpu core ? pipeline .............................................................................. 5 steps ? basic bus cycle ................................. 12.5 ns (at internal 80 mhz) ? logical address space ............................................ 4g-byte linear ? external bus ........................................................ data bus: 16 bits address bus: 24 bits ? internal dram ................................................ 16m bits (2m bytes) ? cache .......................................................... 4k bytes (direct map) ? register configuration ...... general-purpose registers: 32 bits x 16 control registers: 32 bits x 5 ? instruction set ........................ 83 instructions/6 addressing modes ? instruction format .................................................... 16 bits/32 bits ? multiply-accumulate operation unit (dsp function instruction) ? internal memory controller ? programmable i/o ports ? power management function .................................. standby mode /cpu sleep mode ? pll clock generating circuit ................. four-time clock pll circuit ? operation mode .............................................. master/slave mode ? interrupt input ............................................................ ___ ___ int and sbi ? power source .......................................................... 3.3 v (10 %) applications portable equipment, still camera, navigation system, digital instrument, printer, scanner, fa equipment description the M32000D4BFP-80 is a new generation microcomputer with a 32-bit cpu and built-in high capacity dram. using this device it is possible to implement the complex applications of the multimedia age with high performance and low power consumption. the M32000D4BFP-80 contains 2m bytes of dram and 4k bytes of cache memory. the cpu is implemented with a risc architecture and has a high performance figure of 62.9 mips (at an internal clock rate of 80 mhz). memory for main storage is provided internally to the device eliminating external memory and associated control cir- cuits thus reducing overall system noise and power consumption. the cpu, internal dram and cache memory are connected by a 128-bit, 12.5 ns/cycle (at internal 80mhz) internal bus which virtually eliminates transfer bottlenecks in between the cpu and the memory. the M32000D4BFP-80 internally multiplies the frequency of the in- put clock signals by four. for an internal operating frequency of 80 mhz the input clock frequency is 20 mhz. a 16-bit data and 24-bit address bus are the M32000D4BFP-80's external bus and the interface to external peripheral controllers. when the hold state is set, the internal dram can be accessed from an external device. a 3-chip basic system configuration using the M32000D4BFP-80 is the device itself plus an asic as a peripheral controller and a pro- gram rom. execution starts from the reset vector entry on the exter- nal rom after power on, a program requiring high speed execution is then transferred to internal dram and this is then executed. the M32000D4BFP-80 also has a slave mode additional to its master mode. when set to slave mode the M32000D4BFP-80 can be used as a coprocessor. in this mode it does not access its external bus immediatly after reset, but waits for the master to start its operation. mitsubishi microcomputers M32000D4BFP-80
single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 2 pin configuration (top view) note: connect *1 pins to vcc. connect *2 pins to vss. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 M32000D4BFP-80 100-pin qfp/0.65 mm pitch vcc a19 a18 a17 a16 vss a15 a14 *1 vcc stby dc bs pllvcc pllvss pllcap vss clkin *2 pp1 pp0 cs a13 a12 vss a11 a10 a9 a8 vcc vcc a30 a29 a28 a27 vss a26 bch bcl sid vcc r/w *1 vcc vss vss vcc *1 *1 *1 rst m/s a25 a24 vss a23 a22 a21 a20 vcc vss d7 d6 d5 d4 vcc vcc vss vss vcc hreq *1 sbi int hack d3 d2 d1 d0 vss vss d15 d14 d13 d12 vcc burst st vcc vss vcc vss vcc wkup vcc d11 d10 d9 d8 vss single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 3 block diagram M32000D4BFP-80 clkin dram (2m bytes) memory controller pll clock generating circuit 32 bits 32 bits pc alu shift multiply- accumulate unit 32 x 16 bits mul + 56-bit acc register 32 bits x 16 cache memory (4k bytes) instruction queue (128 bits x 2 stages) data selector 32 bits ? 128 bits instruction decoder load/ store 128 128 128 128 128 m32r cpu core pp1 programmable i/o port pp0 a8 - a30 d0 - d15 bcl bs st r/w burst dc hreq hack cs sid external bus interface unit 128 bits ? 16 bits 23 16 m/s rst sbi int wkup 128-bit internal bus stby bch pllcap pllvcc pllvss single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 4 functions function block characteristics cpu core ? bus specification basic bus cycle: 12.5 ns (internal operation at 80 mhz) logical address space: linear 4g bytes ____ ____ external address bus: 24 bits (external output pin: a8 to a30, bch, bcl) external data bus: 16 bits ? implementation: 5-stage pipeline ? core internal: 32 bits ? register configuration general-purpose registers: 32 bits 5 16 control registers: 32 bits 5 5 ? instruction set 16-bit/32-bit instruction format 83 instructions/6 addressing modes ? multiply-accumulate operation built in internal dram ? 16m bits (2m bytes) cache memory ? 4k bytes (internal instruction/data cache mode, instruction cache mode, cache-off mode) memory controller ? cache control ? internal dram control, refresh control ? power management function (standby mode, cpu sleep mode selection control) programmable i/o port ? two programmable i/o ports single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 5 pin function diagram clkin rst M32000D4BFP-80 clock system control vcc vss 16 15 a8 - a30 address bus 23 d0 - d15 data bus 16 hreq hack sid bus control bch bs dc bcl interrupt input pp0 pp1 st r/w burst cs m/s programmable i/o port sbi int wkup stby pllcap pllvcc pllvss single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 6 pin description (1/3) type pin name name i/o function power vcc power source C all power source pins should be connected to vcc. source vss ground C all ground pins should be connected to vss. clock clkin clock input input clock input pin. the M32000D4BFP-80 has an internal pll multiplier circuit, and an input clock which is 1/4 of the internal operating frequency (when the internal operating frequency is 80 mhz, the clkin input is 20 mhz). pllcap c connection C connects a capacitor for the internal pll. for pll pllvcc power source C power source for the internal pll. for pll pllvss ground C ground for the internal pll. for pll system ____ rst reset input internally resets the M32000D4BFP-80. it is also used to return control from standby mode and cpu sleep mode. _ m/s master/slave input sets the M32000D4BFP-80 default operation to either system __ bus master (m/s = "h") or bus slave (m/s = "l"). when the M32000D4BFP-80 is set to bus slave, it does not carry out a reset vector entry fetch after a reset. _ the setting of m/s cannot be changed during operation. keep at either an "h" or an "l" level. ______ wkup wakeup input input pin to request return from standby mode. _____ this is only accepted when stby is "l" level. it generates the wakeup interrupt. _____ stby standby output indicates that the M32000D4BFP-80 has switched to standby mode. an "l" level is output while the device is in standby mode. address a8 to a30 address bus i/o the M32000D4BFP-80 has a 24-bit address (a8 to a31) bus for bus (hi-z)* a 16 mb address space. a31 is not output. during the write cycle, the valid byte positions on the 16-bit data bus are output ____ ____ as bch or bcl. during the read cycle, the 16-bit data bus is read, however,only data in the valid byte positions is transferred to the M32000D4BFP-80. address bus pins are bidirectional. when accessing the internal dram from an external bus master while the M32000D4BFP-80 is in the hold state, input the address from the system bus side. data bus d0 to d15 data bus i/o 16-bit data bus for connecting to external devices. (hi-z)* * (hi-z): this pin goes to high-impedance in the hold state. single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 7 pin description (2/3) type pin name name i/o function bus sid space output space identifier between user space and i/o space. control identifier (hi-z)* sid = "l": user space sid = "h": i/o space sid = undefined: when idle ____ ____ bch, bcl byte control i/o indicates the valid byte positions of transferred data. (hi-z)* ____ ____ bch corresponds to the msb side (d0 to d7), and bcl corresponds ____ to the lsb side (d8 to d15). during a read bus cycle, both bch ____ and bcl are an "l" level. ____ ____ during a write bus cycle, either bch and/or bcl is an "l" level depending on the byte(s) to be written. when accessing the internal dram from an external bus master, the byte control signal is input from the system bus side. __ bs bus start output __ when the M32000D4BFP-80 drives an external bus cycle, bs goes to an "l" level at the start of the bus cycle. __ in burst transfer, bs goes to the "l" level for each transfer cycle. when accessing internal resources such as an internal __ dram or internal i/o register, bs is not output. st bus status output indicates whether the bus cycle that the M32000D4BFP-80 drives is an instruction fetch access cycle or an operand access cycle. st = "l": for instruction fetch access st = "h": for operand access st = undefined: when idle __ r/w read/write i/o __ outputs r/w to identify whether the external bus cycle a read or a write cycle. when accessing the internal dram from an external __ bus master, r/w is input from the external bus. ______ burst burst output the M32000D4BFP-80 drives two consecutive bus cycles to access 32-bit data allocated on the 32-bit word boundary. for instruction fetches, it drives 8 (max.) consecutive cycles (8 cycles in instruction cache mode) to data on the 128-bit boundary. ______ during these consecutive bus cycles, burst goes to "l" level. when accessing 32-bit data, an "l" level followed by an "h" level is output from address a30, because the msb-side 16 bits are accessed prior to the lsb-side 16 bits. when accessing 128-bit data, the addresses are output from an arbitrary 16-bit aligned address and wraparound within a 128-bit aligned boundary. * (hi-z): this pin goes to high-impedance in the hold state. (hi-z)* (hi-z)* (hi-z)* (hi-z)* single-chip 32-bit cmos mic r ocomputer mitsubishi microcomputers M32000D4BFP-80 8 pin description (3/3) type pin name name i/o function bus __ dc* data complete i/o when the M32000D4BFP-80 drives an external bus cycle, it control __ automatically inserts wait cycles until dc is input by the slave (cont.) device in the system bus. when the M32000D4BFP-80 is in the hold state and the internal dram is accessed from an external bus master,the __ M32000D4BFP-80 outputs dc to notify to the external bus master that the bus cycle to the internal dram has been completed. ______ hreq hold input ______ bus right request input pin of the system bus. when hreq is an "l" level, the M32000D4BFP-80 switches to the hold state. _____ hack hold output indicates that the M32000D4BFP-80 has switched to the hold acknowledge state and releases the bus right of the system bus to the requestor. __ cs chip input signal input to the M32000D4BFP-80 when it is in the hold state select to request access to the internal dram from an external bus __ master . when an "l"level is input to cs, the m32000d4 bfp-80 accesses the internal dram at the address input via the address pins. interrupt ___ sbi system input ___ system break interrupt input pin. the sbi is not masked by the ie bit in the psw register. it is also used to return from cpu sleep mode and to request the start of operation in slave mode. ___ int external input external interrupt request input pin. it is also used to return from interrupt cpu sleep mode and to request the start of operation the slave mode. programm- pp0, pp1 port i/o two programmable i/o ports. able i/o port * this pin goes to high-impedance in the hold state. __ __ the dc pin becomes an output pin when the cs signal is input to the M32000D4BFP-80. (hi-z) break interrupt controller single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 9 functional description cpu the m32r cpu has 16 general-purpose registers, 5 control regis- ters, an accumulator and a program counter. the accumulator is of 64-bit width. the registers and program counter are of 32-bit width. general-purpose registers the 16 general-purpose registers (r0 - r15) are of 32-bit width and are used to retain data and base addresses. r14 is used as the link register and r15 as the stack pointer (spi or spu). the link register is used to store the return address when executing a subroutine call instruction. the interrupt stack pointer (spi) and the user stack pointer (spu) are alternatively represented by r15 depending on the value of the stack mode bit (sm) in the processor status word register (psw). control registers there are 5 control registers which are the processor status word register (psw), the condition bit register (cbr), the interrupt stack pointer (spi), the user stack pointer (spu) and the backup pc (bpc). the mvtc and mvfc instructions are used for writing and reading these control registers. r0 r1 r2 r3 r4 r5 r6 r7 31 0 r8 r9 r10 r11 r12 r13 r14 (link register) r15 (stack pointer) 31 0 (see note) note: the interrupt stack pointer (spi) and the user stack pointer (spu) are alternatively represented by r15 depending on the value of the stack mode bit (sm) in the psw. fig. 1 general-purpose registers fig. 2 control registers processor status word register condition bit register interrupt stack pointer user stack pointer backup pc 31 0 cr0 cr1 cr2 cr3 cr6 crn notes 1: crn (n = 0 - 3, 6) denotes the control register number. 2: the mvtc and mvfc instructions are used for writing and reading these control registers. psw cbr spi spu bpc (see notes) single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 10 processor status word register the processor status word register (psw) shows the m32r cpu status. it consists of the current psw field, and the bpsw field where a copy of the psw field is saved when eit occurs. the psw field is made up of the stack mode bit (sm), the interrupt enable bit (ie) and the condition bit (c). the bpsw field is made up of the backup stack mode bit (bsm), the backup interrupt enable bit (bie) and the backup condition bit (bc). note: "init." ...initial state immediately after reset "r" .... : read enabled "w" .... : write enabled d bit name function init. r w 16 bsm (backup sm) saves value of sm bit when eit occurs undefined 17 bie (backup ie) saves value of ie bit when eit occurs undefined 23 bc (backup c) saves value of c bit when eit occurs undefined 24 sm (stack mode) 0: uses r15 as the interrupt stack pointer 0 1: uses r15 as the user stack pointer 25 ie (interrupt enable) 0: does not accept interrupt 0 1: accepts interrupt 31 c (condition bit) indicates carry, borrow and overflow resulting 0 from operations (instruction dependent) fig. 3 processor status word register 16 17 23 24 25 31 15 8 7 0 sm ie c bc bsm bie 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 psw bpsw field psw field single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 11 condition bit register the condition bit register (cbr) is a separate read-only register which contains a copy of the current value of the condition bit (c) in the psw. an attempt to write to the cbr with the mvtc instruction is ignored. interrupt stack pointer, user stack pointer the interrupt stack pointer (spi) and the user stack pointer (spu) retain the current stack address. the spi and spu can be accessed as the general-purpose register r15. r15 switches between repre- senting the spi and spu depending on the value of the stack mode bit (sm) in the psw. backup pc the backup pc (bpc) is the register where a copy of the pc value is saved when eit occurs. bit 31 is fixed at "0". when eit occurs, the pc value immediately before eit occurrence or that of the next in- struction is set. the value of the bpc is reloaded to the pc when the rte instruction is executed. however, the values of the lower 2 bits of the pc become "00" on returning (it always returns to the word boundary). 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cbr c 0 0 0 0 0 31 0 bpc bpc 0 fig. 4 condition bit register, interrupt stack pointer, user stack pointer and backup pc 31 0 spi spu spu 31 0 spi single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 12 accumulator the accumulator (acc) is a 64-bit register used for dsp type func- tions. use the mvtachi and mvtaclo instructions for writing to the accumulator. the high-order 32 bits (bit 0 - bit 31) can be set with the mvtachi instruction and the low-order 32 bits (bit 32 - bit 63) can be set with the mvtaclo instruction. use the mvfachi , mvfaclo and mvfacmi instructions for reading from the accumu- lator. the high-order 32 bits (bit 0 - bit 31) are read with the mvfachi instruction, the low order 32 bits (bit 32 - bit 63) with the mvfaclo instruction and the middle 32 bits (bit 16 - bit 47) with the mvfacmi instruction. program counter the program counter (pc) is a 32-bit counter that retains the ad- dress of the instruction being executed. since the m32r cpu in- struction starts with even-numbered addresses, the lsb (bit 31) is always "0". fig. 5 accumulator 31 0 pc pc 0 fig. 6 program counter 32 48 63 31 16 15 0 47 78 acc (see note) read/write range with mvtaclo or mvfaclo instruction read/write range with mvtachi or mvfachi instruction read range with mvfacmi instruction note: bits 0 - 7 are always read as the sign-extended value of bit 8. an attempt to write to this area is ignored. single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 13 data types signed and unsigned integers of byte (8 bits), halfword (16 bits), and word (32 bits) types are supported as data in the m32r cpu instruc- tion set. a signed integer is represented in a 2's complement format. data formats data size of a register of the m32r cpu is always a word (32 bits). byte (8 bits) and halfword (16 bits) data in memory are sign-extended (the ldb and ldh instructions) or zero-extended (the ldub and lduh instructions) to 32 bits, and loaded into the register. word (32 bits) data in a register is stored to memory by the st in- struction. halfword (16 bits) data in the lsb side of a register is stored to memory by the sth instruction. byte (8 bits) data in the lsb side of a register is stored to memory by the stb instruction. data stored in memory can be one of these types: byte (8 bits), halfword (16 bits) or word (32 bits). although the byte data can be located at any address, the halfword data and the word data can only be located on the halfword bound- ary and the word boundary, respectively. if an attempt is made to access data in memory which is not located on the correct boundary, an address exception occurs. signed byte (8-bit) integer unsigned byte (8-bit) integer signed halfword (16-bit) integer 0 0 0 0 0 0 7 7 15 15 31 31 s s s s: sign bit unsigned halfword (16-bit) integer signed word (32-bit) integer unsigned word (32-bit) integer rn 0 31 < load > byte rn 0 31 halfword rn 0 31 word sign-extention ( ldb instruction) or zero-extention ( ldub instruction) from memory ( ldb , ldub instruction) < store > rn 0 31 byte rn 0 31 halfword rn 0 31 word to memory ( stb instruction) to memory ( sth instruction) to memory ( st instruction) from memory ( ldh , lduh instruction) from memory ( ld instruction) 24 16 24 16 sign-extention ( ldh instruction) or zero-extention ( lduh instruction) fig. 7 data type fig. 8 data format address byte halfword word + 0 + 1 + 2 + 3 031 byte byte byte byte halfword halfword word 7 8 15 16 23 24 single-chip 32-bit cmos mic r ocomputer mitsubishi microcomputers M32000D4BFP-80 14 address space the M32000D4BFP-80 logical address is 32-bit wide and offers 4 gb linear space. the M32000D4BFP-80 has address spaces allo- cated as shown below. the user space is specified by sid = 0 (h'0000 0000 to h'7fff ffff). the area available to the user is 16 mb from address h'0000 0000 to address h'00ff ffff. the i/o space is specified by sid = 1 (h'8000 0000 to h'ff ff ffff). the area available to the user i s 16 mb from address h'ff 00 0000 to address h'ffff ffff. the i/o space cannot be cached. these areas below are allocated in each space. ? user space internal dram area external area ? i/o space user i/o area system area internal i/o area fig. 9 address space h'0000 0000 h'ffff ffff < logical space > eit vector entry (reset interrupt) h'7fff ffff h'8000 0000 i/o space (sid = 1) user space (sid = 0) < physical space > internal dram area (2m bytes) h'0000 0000 h'001f ffff h'0020 0000 h'00ff ffff external area (14m bytes) logical address 0 : h'00 0000 0 : h'1f ffff 0 : h'20 0000 0 : h'ff ffff (16m bytes) (16m bytes) h'ff00 0000 h'ff7f ffff h'ff80 0000 h'ffff ffff h'ffbf ffff h'ffc0 0000 1 : h'00 0000 1 : h'bf ffff 1 : h'ff ffff 1 : h'c0 0000 1 : h'7f ffff 1 : h'80 0000 user i/o area (8m bytes) system area (4m bytes) internal i/o area (4m bytes) physical address (24 bits) eit vector entry (except for reset interrupt) sid physical address (24 bits) sid logical address logical address single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 15 the user i/o area is 8 mb from address h'ff00 0000 to address h'ff7f ffff. when this space is accessed, the control signals to access external devices are output. the system area is 4 mb from address h'ff80 0000 to address h'ffbf ffff. this area is reserved for development tools such as in-circuit emulators or debug moni- tors. the user cannot use this area. the internal i/o area is 4 mb from address h'ffc0 0000 to address h'ffff ffff. the memory controller and programmable i/o port registers are allocated in this area. the internal dram (2 mb) is allocated from address h'0000 0000 to address h'001f ffff. the eit vector entry (other than the reset interrupt) is allocated in the address h'0000 0000 to address h'0000 008f of this area. the internal dram is connected to the m32r cpu via a 4 kb cache memory with a 128-bit bus. when the M32000D4BFP-80 is in the hold state, the internal dram can be accessed from an external bus master by inputting control signals. the external area consists of 14 mb from address h'0020 0000 to address h'00ff ffff. when this space is accessed, the control sig- nals to access external devices are output. the bottom 16 bytes in this area (h'00ff fff0 to h'00ff ffff) are the reset interrupt eit vector entry. fig. 10 internal i/o space memory map h'ffc0 0000 h'ffff ffe0 h'ffff ffe4 h'ffff ffe8 h'ffff fff8 h'ffff fffc logical address 031 +3 address (reserved) +2 address +1 address +0 address ppcr1 ppdr0 memory controller ppdr1 (reserved) mpmr mccr ppcr0 h'ffff ffec mlcr: lock control register mpmr: power management control register mccr: cache control register programmable i/o port ppcr0: programmable i/o port direction control register 0 ppcr1: programmable i/o port direction control register 1 ppdr0: programmable port data register 0 ppdr1: programmable port data register 1 mlcr h'ffff fff4 single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 16 eit events are shown below. ? reserved instruction exception (rie) the reserved instruction exception (rie) occurs when execution of a reserved instruction (unimplemented instruction) is detected. ? address exception (ae) the address exception (ae) occurs if an attempt is made to access an unaligned address with either a load instruction or a store instruc- tion. ? reset interrupt (ri) ___ the reset interrupt (ri) is always accepted when the rst signal is input. it has the highest priority. ? wakeup interrupt (wi) ______ the wakeup interrupt (wi) is accepted when the wkup signal is input while the M32000D4BFP-80 is in standby mode. it is only used to return from standby mode. ? system break interrupt (sbi) ___ the system break interrupt (sbi) is an interrupt request from the sbi pin. it is used when a break in power source or an error from an external watchdog timer is detected. it is also used to return from cpu sleep mode and to start an M32000D4BFP-80 set to slave mode. ? external interrupt (ei) ___ the external interrupt (ei) is an interrupt request from the int pin. it is used by an interrupt from the external peripheral i/o and can be masked by the ie bit in the psw register. it is also used to return from cpu sleep mode and to start an M32000D4BFP-80 set to slave mode. ? trap the trap (trap) is a software interrupt which is generated by ex- ecuting the trap instruction. a total of 16 eit vector entries are available for operands 0 to 15 of the trap instruction. eit while the cpu is executing a program, sometimes it is necessary to suspend execution, because a certain event occurs, and execute another program. these kinds of events are referred to as eit (ex- ception, interrupt, trap). ? exception the event is related to the context being executed. it is generated by errors or violations that occur during instruction execution. with the M32000D4BFP-80, the address exception (ae) and reserved instruc- tion exception (rie) are of this type. ? interrupt the event is not related to the context being executed. it is gener- ated by an external hardware signal. with the M32000D4BFP-80, the external interrupt (ei), system break interrupt (sbi), wakeup in- terrupt (wi) and reset interrupt (ri) are of this type. ? trap this is a software interrupt which is generated by executing the trap instruction. it is intentionally added to the program by the program- mer, as a system call. fig. 11 eit events eit exception reserved instruction exception (rie) address exception (ae) interrupt reset interrupt (ri) wakeup interrupt (wi) system break interrupt (sbi) trap trap (trap) external interrupt (ei) single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 17 internal memory system the memory system built into the M32000D4BFP-80 has the follow- ing characteristics. ?internal 16m-bit (2m-byte) dram ?internal 4k-byte cache memory ?cpu, cache and internal dram are connected by a 128-bit bus ?selectable cache memory operation mode ?internal instruction/data cache mode ?instruction cache mode ?cache-off mode when the internal instruction/data cache mode is selected, the cache memory functions as a cache for both instruction and data from the internal dram, and caches all bus access to the dram. this mode is for a system which uses the internal dram as main memory. trans- fer between the m32r cpu, cache memory and internal dram is always carried out in blocks of 128 bits. caching is carried out by the direct map method. writing is by the copy back method. when the M32000D4BFP-80 access destination is an external space, data transfer between the m32r cpu and the external device is car- ried out via the bus interface unit (biu). the biu has a 128-bit data buffer which converts the bus width between the 128-bit bus in the M32000D4BFP-80 and the external bus. caching is not applicable in this case of data transfer. when accessing the internal dram from an external bus master, and a cache hit occurs (the accessed data is inside the cache), data transfer between the cache memory and the external bus via the biu is carried out. when a cache miss occurs, (the accessed data is not inside the cache) data transfer is carried out between the internal dram and the external bus via the biu without cache replacement. cache control register (mccr) < address: h'ffff ffff> d24 d25 d26 d27 d28 d29 d30 d31 cp cm0 cm1 single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 18 when the instruction cache mode is selected, the cache functions as an instruction cache for the internal dram or the external memory, and caching is carried out for instruction fetch access. this mode is designed for use when an external rom is used as program memory and the internal dram is used as data memory, or when instructions are located in the internal dram. caching is carried out by the direct map method. when instruction codes in the user space are overwrit- ten by the external bus master or another source, instruction code coherency in the cache memory is not guaranteed. furthermore, caching is not applied when accessing the internal dram from the external bus master. when the cache-off mode is selected, the M32000D4BFP-80 inter- nal memory system is configured as follows. in this mode, caching is not applied, and all bus cycles are directly to the internal dram or external bus. fig. 14 instruction cache mode fig. 15 cache-off mode external bus (16 bits) 16 external bus interface M32000D4BFP-80 128 aaaa aaaa instruction cache biu 128 dram cpu aaaaa aaaaa aaaaa aaaaa 128 external bus (16 bits) 16 external bus interface M32000D4BFP-80 128 dram biu cpu single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 19 bus interface unit (biu) the M32000D4BFP-80 has the following signals related to the exter- nal bus. ? address (a8 to a30) the M32000D4BFP-80 has a 24-bit address bus (a8 to a31) corre- sponding to a 16 mb address space. of these, a31 (the lsb) is not output externally. in write cycles, the validity of the two bytes output ___ ___ on the 16-bit data bus is indicated by bch and/or bcl. in read cycles, the 16-bit data bus is always read, however, only data in the valid byte position in the M32000D4BFP-80 is transferred. the ad- dress pins are bidirectional. if the M32000D4BFP-80 is in the hold state and the internal dram is accessed from an external bus mas- ter, the address signal is input from the system bus side. ? space identifier (sid) the space identifier is used to specify user space and i/o space. user space: sid = "l" i/o space: sid = "h" hold: sid = high-impedance idle: sid = undefined ___ ___ ? byte control (bch, bcl) byte control signals indicate the byte position of valid data trans- ___ ferred of the external bus cycle. bch corresponds to the msb side ________ (d0 to d7), and bcl corresponds to the lsb side (d8 to d15). dur- ___ ___ ing the read bus cycle, both bch and bcl are an "l" level. during ___ ___ the write bus cycle, bch and/or bcl go to an "l" level depending on the bytes to be written. if the M32000D4BFP-80 is in the hold state and the internal dram is accessed from an external bus master, the byte control signal is input from the system bus side. ? data bus (d0 to d15) the M32000D4BFP-80 has a 16-bit data bus to access external de- vices. if the M32000D4BFP-80 is in the hold state and the internal dram is accessed from an external bus master, the data bus is used as a data i/o bus from the system bus side. __ ? bus start (bs) when the M32000D4BFP-80 drives the bus cycle to the system bus, __ an "l" level is output to bs at the start of the bus cycle. also, for a __ __ burst transfer, the bs signal is output for each transfer cycle. the bs signal is not output when accessing internal resources such as the internal dram or internal i/o registers. ? bus status (st) the st signal identifies whether the bus cycle the m32000d4bfp- 80 is driving is an instruction fetch cycle or an operand access cycle. instruction fetch access: st = "l" operand access: st = "h" hold: st = high-impedance idle: st = undefined __ ? read/write (r/w) __ the M32000D4BFP-80 outputs a r/w signal to identify whether the external bus cycle is a read or write operation. when accessing the __ internal dram from an external bus master, a r/w signal is input from the system bus side. __ read bus cycle: r/w = "h" __ write bus cycle: r/w = "l" ______ ? burst (burst) the M32000D4BFP-80 drives two consecutive bus cycles to access 32-bit data located on the 32-bit boundary. in instruction fetching, it drives a maximum of 8 (fixed to 8 cycles in instruction cache mode) consecutive read cycles to access data located on the 128-bit bound- ary. while driving these consecutive bus cycles, the m32000d4bfp- ______ 80 outputs "l" level to burst. when accessing 32-bit data, the ad- dress of the msb-side 16 bits are output before the address of the lsb side 16 bits. when accessing 128-bit data, the addresses are output for every access cycle from the arbitrary 16-bit aligned ad- dresses to wraparound within the 128-bit boundary. __ ? data complete (dc) when starting an external bus cycle, the M32000D4BFP-80 auto- __ matically inserts wait cycles until the dc signal is input from external. __ wait control using the dc signal is effective also for bus cycles dur- ing burst transfer. when the M32000D4BFP-80 is in the hold state __ __ and if the cs signal is input, the M32000D4BFP-80 outputs the dc signal to notify the external bus master that internal dram access is complete. _____ _____ ? hold control (hreq, hack) the hold state is the state when the external bus access stops and all pins go to a high-impedance state. however, the internal dram can be accessed while the external bus is in the hold state. to put _____ the M32000D4BFP-80 into the hold state, input an "l" level to hreq. when the hold request is accepted and the M32000D4BFP-80 en- _____ ters the hold state, an "l" level is output from hack. single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 20 __ ? internal dram access control (cs) __ the internal dram can be accessed when cs is driven to an "l" ____ level after the M32000D4BFP-80 enters the hold state (hack = "l"). to access the internal dram from external, the following signals from the system bus side should be controlled. ? a8 to a30 input internal dram addresses to be read or written. ___ ___ ? bch, bcl specify the byte position of data to be written into the internal ___ ___ dram. bch corresponds to the msb side (d0 to d7), and bcl corresponds to the lsb side (d8 to d15). __ ? r/w ___ specify read or write operation. when reading, r/w = "h". when __ writing, r/w = "l". ? d0 to d15 16-bit data i/o bus. _____ ? dc this signal notifies to an external bus master that the internal dram access is complete. when access is complete, an "l" _____ level is output to dc. read and write operations of the M32000D4BFP-80 are carried out ___ _______ _______ _____ using the address bus, data bus, and the r/w, bch, bcl and dc ___ signals. when reading, the r/w signal goes to an "h" level, and the _______ _______ bch and bcl signals go to an "l" level. the cpu reads the data in the valid byte positions. when writing, an "l" level is output from r/ ___ _______ _______ w, and bch and bcl are output according to the valid byte posi- tions, so as to specify the byte positions for writing into an external device. pin name pin condition or operation a8 - a30, sid, high-impedance ____ ____ bch, bcl __ ___ ______ st, r/w, bs, burst d0 - d15 output when internal dram is read __ by an external bus master (cs = "l", __ r/w = "h"), otherwise high-impedance __ dc output when internal dram is accessed by an external bus master __ (cs = "l"), otherwise high-impedance _____ hack output "l" other pins normal operation table 1 pin condition in hold state fig. 16 read/write timing (two no-wait accesses) idle read "h" "h" clkin bs a8 - a30 sid, st bch, bcl burst d0 - d15 dc r/w idle read idle write idle write clkin bs a8 - a30 sid, st bch, bcl burst d0 - d15 dc r/w "h" "hi-z" "hi-z" "hi-z" "hi-z" note: "hi-z" means high-impedance, and indicates sampling timing. single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 21 fig. 18 automatic idle cycle insertion between consecutive read and write cycles __ when an "l" level is input to dc, the next bus cycle is processed and wait cycles are inserted until this point. when a write cycle comes immediately after a read cycle, the M32000D4BFP-80 inserts an idle cycle to prevent a collision with data on the system bus. the same applies to write cycles (burst write access) immediately after a burst read cycle. fig. 17 read/write timing (two one-wait accesses) "h" "h" idle read clkin bs a8 - a30 sid, st bch, bcl burst d0 - d15 dc r/w idle read "h" idle write idle write clkin bs a8 - a30 sid, st bch, bcl burst d0 - d15 dc r/w "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" note: "hi-z" means high-impedance, and indicates sampling timing. keep dc signal at the "h" level when waits are inserted. "h" idle clkin bs a8 - a30 sid, st bch, bcl burst d0 - d15 dc r/w idle read write idle "hi-z" "hi-z" "hi-z" note: "hi-z" means high-impedance, and indicates sampling timing. single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 22 ______ the M32000D4BFP-80 outputs the burst signal and carries out a burst transfer when reading "the word-size data aligned on the 32-bit boundary" or "a maximum 4 words of instructions aligned on the 128- ______ bit boundary". the burst signal is synchronized with the clkin falling edge of the first bus access cycle and output "l" level. it re- turns to an "h" level synchronized with the first clkin falling edge of the last bus access cycle. addresses a8 to a30 are output for each cycle. when burst reading 32-bit data, the msb-side 16-bit read bus cycle is carried out first followed by the lsb-side 16-bit read bus cycle. when the cache memory operation mode is the instruction cache mode, and burst reading of the instructions within the 128-bit bound- ary for cache replacement occurs, the bus cycle is driven a fixed 8 times from an arbitrary 32-bit boundary address and to wraparound within the 128-bit boundary. when other than the instruction cache mode is selected and burst reading a set of instructions of less than 128 bits, consecutive bus cycles are driven from an arbitrary 32-bit boundary address as the top to the 128-bit line (a28 to a30 = "111"). fig. 20 4-word (128-bit) burst read timing (1-0-0-0-0-0-0-0 wait) fig. 19 1-word (32-bit) burst read timing (1-0 wait) "h" idle clkin bs a8 - a30 sid, st bch, bcl burst d0 - d15 dc r/w burst read (1 word) idle "hi-z" "hi-z" note: "hi-z" means high-impedance, and indicates sampling timing. wait cycles can be inserted even when burst transferring by setting dc = "h". wait cycles can be inserted even when burst transferring by setting dc = "h". "h" idle clkin bs a8 - a30 sid, st bch, bcl burst d0 - d15 dc r/w burst read ( 4 words) idle "hi-z" note: "hi-z" means high-impedance, and indicates sampling timing. single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 23 when writing word-size data aligned on the 32-bit boundary, the M32000D4BFP-80 carries out a burst-transfer by outputting the ______ burst signal. when burst-writing 32-bit data, the msb-side 16-bit write bus cycle is driven first, followed by the lsb-side 16-bit write ______ bus cycle. the burst signal is synchronized with the clkin falling edge of the first bus access cycle, and "l" level is output. it returns to "h" level in synchronization with the clkin falling edge of the last bus access cycle. addresses a8 to a30 are output for each cycle. _____ when an "l" level is input to hreq, the M32000D4BFP-80 switches _____ to the hold state and outputs an "l" level to hack. while the M32000D4BFP-80 is in the hold state, bus related pins go to a high impedance state, and data transfer is carried out on the system bus. _____ to return to normal operation mode from the hold state, the hreq signal should be changed to an "h" level. fig. 21 1-word (32-bit) burst write timing (1-0 wait) fig. 22 bus arbitration timing "hi-z" "hi-z" "hi-z" (see note 2) "hi-z" "hi-z" "hi-z" "hi-z" notes 1: before switching to the hold state, an idle cycle of 1 clkin clock period is always inserted. after returning from the hold state, an idle cycle of 1 to 5 clkin clock periods is always inserted. 2: "hi-z" means high impedance, and indicates sampling timing. 3: while the M32000D4BFP-80 is in the hold state, the dc signal is driven and output when the cs signal is input. (see note 2) (see note 3) write clkin hreq bch, bcl d0 - d15 dc r/w idle hold shift hold return idle hack a8 - a30 sid, st (see note 1) (see note 1) bs burst idle clkin bs a8 - a30 sid,st bch, bcl burst d0 - d15 dc r/w burst write (1 word) idle "hi-z" "hi-z" note: "hi-z" means high-impedance, and indicates sampling timing. wait cycles can be inserted even when burst transferring by setting dc = "h". single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 24 when the M32000D4BFP-80 is in the hold state and an "l" level is __ input to cs, the M32000D4BFP-80 interprets it as a bus access re- __ quest to the internal dram. in this case, when the r/w signal is an "h" level, the memory controller drives a read cycle to the internal dram. in the read cycle, the 16-bit data for the address specified ____ with a8 to a30, is output from d0 to d15 regardless of the bch and ___ __ bcl settings. also the dc signal is output. the M32000D4BFP-80 reads 128 bits of data from the block on the 128-bit boundary including the requested address into the 128-bit buffer of the bus interface unit. 3 to 7 clkin clock periods are neces- sary for the first bus access, however, when reading consecutive address within the 128-bit boundary, the subsequent read bus cycles are completed in 1 clkin clock period because a read from the in- ternal dram does not take place. once the external bus master read cycle has been driven, it cannot __ be aborted. when an "l" level is input to cs and an access has started, the values of this and other control signals should be held __ __ during the wait cycles (that is while dc = "h"). after dc outputs an __ "l" level (access complete), return cs to the "h" level between the clkin falling edge corresponding to the last read cycle and the fol- ______ lowing clkin falling edge. return hreq to the "h" level to return the M32000D4BFP-80 to the normal operation mode from the hold __ state either at the same time as or after cs is returned to the "h" level. fig. 23 read bus cycle to internal dram ("l" output) "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" ] hreq bch, bcl d0 - d15 dc r/w hold shift hold return hack a8 - a30 cs read read read read note: "hi-z" means high impedance, and indicates sampling timing. clkin the value of the r/w signal that controls the data direction of the bus interface cannot be changed during cs="l". hold this value while cs="l". also, where marked above with ] , 3 to 7 clkin clock periods are necessary for the first read operation (also when reading crosses an 128-bit boundary) when reading from the internal dram. hold the input value of the address or other control signals during these wait cycle periods (dc = "h"). consecutive read operations within an 128-bit boundary are completed in 1 clkin clock period. during these wait cycle period, cs cannot be returned to an "h" level (the access cannot be aborted). cs can only be returned to an "h" level after dc is driven to "l". single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 25 ("l" output) ("l" output) "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" ] clkin hreq bch, bcl d0 - d15 dc r/w hold shift hold return hack a8 - a30 cs write write write write note: "hi-z" means high impedance, and indicates sampling timing. the value of the r/w signal that controls the data direction of the bus interface cannot be changed during cs="l". hold this value while cs="l". also, where marked above with ] , 3 to 7 clkin clock periods are necessary for writing operation to internal dram crossing an 128-bit boundary. hold the input value of the address or other control signals during these wait cycle periods (dc = "h"). consecutive writing operations within an 128-bit boundary are completed in 1 clkin clock period. during these wait cycle period, cs cannot be returned to "h" level (the access cannot be aborted). cs can only be returned to a "h" level after dc is driven to "l". when the M32000D4BFP-80 is in the hold state and an "l" level is __ input to cs, the M32000D4BFP-80 interprets it as a bus access re- __ quest to the internal dram. in this case, when the r/w signal is at an "l" level, the memory controller drives a write cycle to the internal ____ ___ dram. byte data control is specified by the bch and bcl signals. ____ only data in the byte positions for which an "l" level is input to bch ___ __ or bcl are written. when writing is complete, an "l" level dc signal is output. the M32000D4BFP-80 stores the requested data in the 128-bit data buffer of the biu, before writing to the internal dram. this reduces the number of accesses to the internal dram when a request to writing to consecutive addresses is made, and improves bus cycle throughput. consecutive write cycles within an 128-bit boundary are completed in 1 clkin clock period. 3 to 7 clkin clock periods are necessary for a write access crossing an 128-bit bound- ary when writing to the internal dram. once the external bus master write cycle has been driven, it cannot be aborted. when an "l" level __ is input to cs and an access has started, the values of this and other __ control signals should be held during the wait cycles (that is while dc __ __ = "h"). after dc outputs an "l" level (access complete), return cs to the "h" level between the clkin falling edge corresponding to the ______ last write cycle and the following clkin falling edge. return hreq to the "h" level to return the M32000D4BFP-80 to the normal opera- __ tion mode from the hold state either at the same time as or after cs is returned to the "h" level. when the external bus master makes an access, the value of the __ r/w signal that controls the data direction of the bus interface can- __ not be changed during cs="l". therefore, read cycles and write cycles __ cannot be mixed while cs = "l". when starting a write cycle follow- ing after a read cycle and starting a read cycle following a write cycle, __ keep the cs signal at an "h" level for at least 1 clkin. fig. 24 write bus cycle to internal dram fig. 25 read/write bus cycle to internal dram clkin hreq bch, bcl d0 - d15 dc r/w hold shift hold return hack a8 - a30 cs ("l" output) read cs = "h" write ("l" output) "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" "hi-z" ] "hi-z" "hi-z" note: "hi-z" means high-impedance, and indicates sampling timing. also, where marked above with ] , keep cs signal to "h" at least 1 clkin when starting a write bus cycle after a read bus cycle or a read bus cycle after a write bus cycle. "hi-z" single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 26 M32000D4BFP-80 (master) rom asic pp0 m/s m/s hreq int M32000D4BFP-80 (slave) hack hreq hack bus arbiter int master/slave mode _ the M32000D4BFP-80 has an m/s (master/slave) pin for multipro- cessor configuration use. _ ?master mode (m/s = "h") _ this is normal operation mode. set the m/s pin to an "h" level. it is used when the M32000D4BFP-80 is used as the main cpu in a system. _ ?slave mode (m/s = "l") this operation mode is for when the M32000D4BFP-80 is used as a _ coprocessor. set the m/s pin to an "l" level. when set to slave mode, the M32000D4BFP-80 does not start operation even after a reset, until an interrupt request or the sbi is input. processing is carried out by communicating with the master M32000D4BFP-80, using the two programmable i/o ports and the external interrupt signal. d24 d25 d26 d27 d28 d29 d30 d31 lm lock control register (mlcr) < address: h'ffff fff7> fig. 26 lock control register ______ 0: hreq exclusive lock mode ___ 1: cs exclusive lock mode r = 0 ... "0" when reading r = ... read enabled w = ... write enabled w = : write disabled single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 27 in standby mode, all clock supply stops and only the contents of the internal dram are retained. the power requirement is only that which the internal dram needs for refreshing itself. when set to standby mode, the M32000D4BFP-80 waits for the current bus operation to be completed. it then purges the cache memory and switches the internal dram to self-refresh mode. after that, the pll and all clock _____ supplies stop and the stby signal goes to an "l" level to indicate the _____ completion of the switch to standby mode. input an "l" level to wkup ___ or rst to return from standby mode to normal operation mode. the contents of the internal dram are retained upon return using the _____ wkup signal. in cpu sleep mode, clock supply to the m32r cpu stops. in this mode, the internal dram, cache memory, memory controller and external bus interface continue to operate and the internal dram ___ ___ can be accessed from the external bus. input an "l" level to int, sbi ___ or rst to return to normal operation mode from cpu sleep mode. the contents of the cache memory, internal dram, general-purpose registers and programmable i/o control register are retained upon ___ ___ return using the int or sbi signals. power management function the M32000D4BFP-80 has the following two low-power consump- tion modes. ?standby mode ?cpu sleep mode power management (mpmr) < address: h'ffff fffb> d24 d25 d26 d27 d28 d29 d31 pm1 pm0 d30 single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 28 internal resources state dram undefined cache memory invalid (purged all) general purpose undefined registers (r0 - r15) control registers psw (cr0) b'0000 0000 0000 0000 ??00 000? 0000 0000 (bsm, bie, and bc are undefined) cbr (cr1) h'0000 0000 spi (cr2) undefined spu (cr3) undefined bpc (cr6) undefined pc master mode: execute from address h'7fff fff0 slave mode: wait for interrupt input at address h'7fff fff0 ? execute from address h'0000 0010 ___ by inputting sbi signal ? execute from address h'0000 0080 ___ by inputting int signal acc (accumulator) undefined i/o registers ppcr0, ppcr1 h'00 (input) ppdr0, ppdr1 b'0000 000? (depends on input pin state) mlcr _____ h'00 (hreq exclusive lock mode) mpmr h'00 (normal operation) mccr h'01 (cache-off mode) programmable i/o port the M32000D4BFP-80 has two programmable i/o ports (pp0, pp1). each port can be set as input or output. reset ____ when an "l" level is input to rst, the M32000D4BFP-80 switches to the reset state. the reset state is released when an "h" level is input ____ to rst, and the program is executed from the eit vector entry of the reset interrupt. all internal resources including the internal pll (4x clock generator) are initialized. in order to stabilize pll oscillation, ____ the "l" input to rst should last a minimum of 2 ms after the clock input to clkin stabilizes and vcc stabilizes to the specified voltage level. single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 29 clock generating circuit the M32000D4BFP-80 has a clock multiplier circuit and operates at four times the input frequency. the internal operation frequency be- comes 80 mhz when a 20 mhz clock is input to clkin. a capacitor (c) should be connected to the pllcap pin, and the clock is input to the clkin pin. the pllvcc and pllvss pins should be connected to the power source or the ground, respectively. addressing mode m32r family supports the following addressing modes. < register direct > the general-purpose register or the control register to be processed is specified. < register indirect > the contents of the register specify the address in memory to be accessed. this mode can be used by all load/store instructions. < register relative indirect > (the contents of the register) + (16-bit immediate value which is sign- extended to 32 bits) specify the address in memory to be accessed. < register indirect and register update > ? 4 is added to the register contents (the contents of the register before update specify the address in memory to be accessed) [ ld instruction] ? 4 is added to the register contents (the contents of the register after update specify the address in memory to be accessed) [ st instruction] ? 4 is subtracted from the register contents (the contents of the register after update specify the address in memory to be accessed) [ st instruction] < immediate > the 4-, 5-, 8-, 16- or 24-bit immediate value. < pc relative > (the contents of pc) + (8, 16, or 24-bit displacement which is sign- extended to 32 bits and 2 bits left-shifted) specify the address in memory to be accessed. fig. 32 oscillation circuit M32000D4BFP-80 a 18 (clkin) a 16 (pllcap) 15 (pllvss) a c a 14 (pllvcc) vcc pll clock generating circuit clock input recommended values in circuit c : 1000 pf single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 30 instruction set a total of 83 instructions are implemented. single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 31 single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 32 power source voltage input voltage output voltage power consumption operating temperature storage temperature absolute maximum ratings ratings topr = 25 c conditions parameter vcc vi vo pd topr tstg symbol unit v v v mw c c min. max. C0.5 C0.5 C0.5 0 C65 4.6 4.6 4.6 1000 70 150 recommended operating conditions (vcc = 3.3 v 0.3 v, topr = 0 to 70 c unless otherwise noted) vcc vih vil ioh (see note) iol (see note) cl ratings max. 3.6 vcc+0.3 vcc+0.3 0.8 0.2vcc 2 2 50 v v v v v ma ma pf symbol parameter unit min. 3.0 2.0 0.8vcc C0.3 C0.3 power source voltage "h" input voltage all inputs except following ____ rst pin "l" input voltage all inputs except following ____ rst pin "h" output current "l" output current output load capacity typ. note : ioh and iol represent the maximum values of dc current load. intermittent current that is generated during output need not to be considered as long as the output load capacity is within the specified range. single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 33 ioh = C2 ma iol = 2 ma vo = 0 to vcc vih = 0 to vcc +0.3 v vih = 0 to vcc +0.3 v average in normal operation mode vcc = 3.3 v (see note 1) average in cpu sleep mode vcc = 3.3 v average in standby mode vcc = 3.3 v (see note 2) all pins "h" output voltage "l" output voltage output current in off state "h" input current "l" input current power source current pin capacitance voh vol ioz iih iil icc c dc characteristics electrical characteristics (vcc = 3.3 v 0.3 v, topr = 0 to 70 c unless otherwise noted) ratings max. 0.4 10.0 10.0 C10.0 260 205 2000 15 v v a a a ma ma a pf symbol parameter unit min. 2.4 C10.0 test conditions typ. 165 120 note 1 :all pin outputs are in no-load condition. 2 :topr = 25c single-chip 32-bit cmos mic r ocomputer mitsubishi microcomputers M32000D4BFP-80 34 min. max. 5 2 5 2 ac characteristics timing requirements (vcc = 3.3 0.3 v, cl = 50 pf, topr = 0 to 70 c unless otherwise noted) limits symbol parameter min. input rise transition time input fall transition time test conditions cmos input ____ rst pin cmos input ____ rst pin (1) input transition time tr(input) tf(input) unit ns ms ns ms reference number 1 2 limits symbol parameter clock input cycle time external clock input "h" pulse width external clock input "l" pulse width external clock input rising time external clock input falling time reset input "l" pulse width wakeup input "l" pulse width (2) clock, reset and wakeup timing tc(clkin) tw(clkinh) tw(clkinl) tr(clkin) tf(clkin) tw(rst) tw(wkup) max. 80 5 5 unit ns ns ns ns ns ms ms reference number 50 1/4clkin 1/4clkin 2 2 5 6 7 8 9 10 11 limits symbol parameter min. data input set-up time before clkin data input hold time after clkin __ dc input "h" set-up time before clkin __ dc input "h" hold time after clkin __ dc input "l" set-up time before clkin __ dc input "l" hold time after clkin test conditions (3) read and write timing max. unit ns ns ns ns ns ns reference number 5 2 5 2 5 2 30 31 36 37 38 39 tsu(d-clkin) th(clkin-d) tsu(dch-clkin) th(clkin-dch) tsu(dcl-clkin) th(clkin-dcl) test conditions single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 35 (4) arbitration and external bus master read/write timing limits symbol min. test conditions max. unit ns ns ns ns ns ns ns ns 5 2 5 2 5 2 5 2 40 41 48 49 50 51 52 53 tsu(hreq-clkin) th(clkin-hreq) tsu(cs-clkin) th(clkin-cs) tsu(a-clkin) th(clkin-a) tsu(d-clkinl) th(clkinl-d) parameter _____ hreq input set-up time before clkin _____ hreq input hold time after clkin __ cs input set-up time before clkin __ cs input hold time after clkin address input set-up time before clkin address input hold time after clkin data input set-up time before clkin data input hold time after clkin limits symbol parameter min. ___ int input pulse width (see note) ___ sbi input pulse width (see note) test conditions (5) interrupt input timing tw(int) tw(sbi) max. unit ns ns reference number tc(clkin) tc(clkin) 63 64 ___ ___ note: both int and sbi are level-sense inputs. keep them at an "l" level until the interrupt is accepted. (6) i/o port timing limits symbol parameter min. port input "l" pulse width port input "h" pulse width test conditions tw(portinl) tw(portinh) max. unit ns ns reference number 25 25 69 70 reference number single-chip 32-bit cmos mic r ocomputer mitsubishi microcomputers M32000D4BFP-80 36 switching characteristics (vcc = 3.3 0.3 v, cl = 50 pf, topr = 0 to 70 c unless otherwise noted) limits symbol parameter test conditions (1) output transition time tr(output) tf(output) reference number 3 4 min. unit max. 8 8 typ. output rising transition time output falling transition time ns ns (2) read and write timing limits symbol td(clkin-bshx) td(clkin-bsl) td(clkin-bslx) td(clkin-bsh) td(clkin-av) td(clkin-ax) td(clkin-bcv) td(clkin-bcx) td(clkin-sidv) td(clkin-sidx) td(clkin-stv) td(clkin-stx) td(clkin-rwv) td(clkin-rwx) td(clkin-bursthx) td(clkin-burstl) td(clkin-burstlx) td(clkin-bursth) td(clkin-dzx) td(clkin-dv) td(clkin-dvx) td(clkin-dxz) reference number 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 32 33 34 35 min. unit max. __ bs = "h" effective time after clkin __ bs = "l" delay time after clkin __ bs = "l" effective time after clkin __ bs = "h" delay time after clkin address delay time after clkin address effective time after clkin ___ _ ___ bch, bcl delay time after clkin ___ _ ___ bch, bcl effective time after clkin sid delay time after clkin sid effective time after clkin st delay time after clkin st effective time after clkin __ r/w delay time after clkin __ r/w effective time after clkin ______ burst = "h" effective time after clkin ______ burst = "l" delay time after clkin ______ burst = "l" effective time after clkin ______ burst = "h" delay time after clkin data output enable time after clkin data output delay time after clkin data output effective time after clkin data output disable time after clkin parameter ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 tc(clkin)/4+8 10 10 10 10 10 8 8 15 16 test conditions 0 tc(clkin)/4 0 0 0 0 0 0 0 0 0 single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 37 (3) arbitration and external bus master read/write timing limits symbol test conditions td(clkin-hackhx) td(clkin-hackl) td(clkin-hacklx) td(clkin-hackh) td(clkin-az) td(clkin-azx) td(clkin-dzx) td(clkin-dv) td(clkin-dxz) td(clkin-dvx) td(cs-dczx) td(clkin-dchx) td(clkin-dcl) td(clkin-dcxz) td(clkin-dclx) 42 43 44 45 46 47 54 55 56 57 58 59 60 61 62 max. _____ hack = "h" effective time after clkin _____ hack = "l" delay time after clkin _____ hack = "l" effective time after clkin _____ hack = "h" delay time after clkin address output disable time after clkin address output enable time after clkin data output enable time after clkin data output delay time after clkin data output disable time after clkin data output effective time after clkin __ __ dc output enable time after cs __ dc = "h" effective time after clkin __ dc = "l" delay time after clkin __ dc output disable time after clkin __ dc = "l" effective time after clkin parameter 8 8 16 15 16 12 12 min. 0 0 0 0 0 0 0 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns unit reference number (4) standby timing limits symbol test conditions td(clkin-stbyhx) td(clkin-stbyl) td(clkin-stbylx) td(clkin-stbyh) reference number 65 66 67 68 min. unit max. parameter ns ns ns ns tc(clkin)n/4+15 tc(clkin)n/4+15 _____ stby = "h" effective time after clkin _____ stby = "l" delay time after clkin (see note) _____ stby = "l" effective time after clkin _____ stby = "h" delay time after clkin (see note) 0 0 _____ note: the stby signal is synchronized with the internal clock, therefore its timing changes at 0, 90, 180 and 270 (n=0, 1, 2, 3) de gree phase of clkin. limits symbol parameter min. port output "l" pulse width (see note) port output "h" pulse width (see note) test conditions (5) i/o port timing tw(portoutl) tw(portouth) max. unit ns ns reference number 10 10 71 72 note: the minimum pulse width value is that where the output is changed within 1 clock of the internal clock. software processing ti me to write to the port data register is not included. single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 38 fig. 34 output switching characteristic measurement circuit c l = 50 pf cmos output cmos output ( during floating delay time measurement) measured pin c l = 50 pf measured pin 0.5v cc 1.0 k w fig. 35 input waveform and timing reference point during characteristic measurement fig. 36 output timing measurement point during characteristic measurement timing reference point 0.8vcc 0.2vcc cmos output (when not specified) 0.9vcc cmos output (during floating delay time measurement) 0.1vcc 0.6vcc 0.4vcc "h" ? "z" "l" ? "z" "z" ? "h" "z" ? "l" timing reference point (when not specified) "h" input level "l" input level vcc 0.0 v 0.9vcc 0.1vcc 0.8vcc 0.9vcc 0.1vcc 0.2vcc cmos input schmitt trigger input "h" input level "l" input level vcc 0.0 v clkin input "h" input level "l" input level single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 39 cmos input (except for schmitt trigger input and clkin input) schmitt trigger input (rst) 0.8vcc 0.9vcc 0.1vcc 0.2vcc t r(input) t f(input) t r(input) t f(input) 1 1 2 2 output pin 0.8vcc 0.2vcc t r(output) t f(output) 3 4 fig. 37 input transition time fig. 38 output transition time fig. 39 clock reset and wakeup timing t w(rst) rst 0.5vcc 0.8vcc 0.2vcc t w(clkinh) t w(clkinl) t r(clkin) t f(clkin) clkin (input) (input) t c(clkin) 5 6 7 8 9 10 t w(wkup) wkup (input) 11 *1 the wkup and rst signals can be input asynchronously. when returning from standby mode, the same timing applies. *1 *1 single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 40 fig. 40 read/write timing clkin (input) (output) (output) 0.5 vcc (input) (output) d0 to d15 d0 to d15 (input) t d(clkin-dv) t d(clkin-dzx) t d(clkin-dvx) t d(clkin-dxz) t su(dcl-clkin) t h(clkin-dcl) t su(d-clkin) t h(clkin-d) bs bch, bcl dc 13 15 30 31 32 33 34 35 38 39 (output) a8 to a30 t d(clkin-av) 16 (output) t d(clkin-stv) sid, st 22 (output) t d(clkin-rwv) r/w 24 (output) burst t d(clkin-bsh) t d(clkin-burstl) 27 t d(clkin-bursth) 29 t d(clkin-bsl) t d(clkin-bcv) 18 t d(clkin-sidv) 20 12 t d(clkin-bshx) 14 t d(clkin-bslx) t d(clkin-ax) 17 t d(clkin-bcx) 19 t d(clkin-stx) 23 t d(clkin-sidx) 21 t d(clkin-rwx) 25 t d(clkin-bursthx) 26 t d(clkin-burstlx) 28 t su(dch-clkin) t h(clkin-dch) 36 37 *1 the set up/hold of dc = "h" may vary depending on the wait cycle insertion. *1 *1 *2 all switching characteristics and timing requirements based on the falling edge of clkin are calculated according to the internal clkin (duty ratio is 50%) . when designing external peripheral circuits, the correction for the duty cycle of the actual clkin is necessary. ?minimum value of td(clkin-bslx) = (value in table) ?(correction value) = 12.5 ?(50 x 5/100) = 10 [ns] ?maximum value of td(clkin-bsh) = (value in table) + (correction value) = (50/4 + 8) + (50 x 5/100) = 23 [ns] *2 *2 *2 *2 *2 *2 [example] bs signal transition ("l" ? "h") when inputting 20mhz clock whose duty ratio is 45 - 55% ( 5%) to clkin: 0.5 vcc single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 41 fig. 41 bus arbitration timing clkin hreq hack a8 to a30, sid, st, bs, bch, bcl, r/w, burst (output) (input) (input) (output) *1 the hreq signal can be input asynchronously. *2 all switching characteristics and timing requirements based on the falling edge of clkin are calculated according to the internal clkin (duty ratio is 50%) . when designing external peripheral circuits, the correction for the duty cycle of the actual clkin is necessary. ?minimum value of td(clkin-hackhx) = (value in table) ?(correction value) = 0 ?(50 x 5/100) = ?.5 [ns] ?maximum value of td(clkin-hackl) = (value in table) + (correction value) = 8 + (50 x 5/100) = 10.5 [ns] [example] hack signal transition ("h" ? "l") when inputting 20 mhz clock whose duty ratio is 45 - 55% ( 5%) to clkin: 0.5vcc 0.5vcc t d(clkin-hackl) t d(clkin-hackhx) t d(clkin-hackh) t d(clkin-hacklx) t d(clkin-azx) t d(clkin-az) t su(hreq-clkin) 41 42 43 44 45 46 47 *1 *1 t h(clkin-hreq) 40 *2 *2 *2 *2 single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 42 fig. 42 external bus master read/write timing clkin (input) (input) 0.5 vcc (input) (output) d0 to d15 d0 to d15 (input) t h(clkinl-d) hreq r/w 40 52 53 54 55 (output) t su(hreq-clkin) hack 41 43 t d(clkin-hackl) 45 (input) cs 48 t su(cs-clkin) 49 t h(clkin-cs) t d(clkin-dv) t d(clkin-dzx) 50 t su(a-clkin) 51 t h(clkin-a) (output) dc 60 t d(clkin-dcl) 59 t d(clkin-dchx) 42 t d(clkin-hackhx) 44 58 t d(cs-dczx) t d(clkin-hackh) t d(clkin-hacklx) t h(clkin-hreq) 50 51 (input) a8 to a30 bch, bcl 50 51 50 51 48 49 t su(d-clkinl) 48 49 t d(clkin-dxz) t d(clkin-dvx) 56 57 t d(clkin-dclx) t d(clkin-dcxz) 58 60 59 62 61 62 61 *1 all switching characteristics and timing requirements based on the falling edge of clkin are calculated according to the internal clkin (duty ratio is 50%) . when designing external peripheral circuits, the correction for the duty cycle of the actual clkin is necessary. ?minimum value of tsu(cs-clkin) = (value in table) + (correction value) = 5 + (50 x 5/100) = 7.5 [ns] ?minimum value of th(clkin-cs) = (value in table) + (correction value) = 2 + (50 x 5/100) = 4.5 [ns] *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 [example] cs signal transition ("l" ? "h") when inputting 20 mhz clock whose duty ratio is 45 - 55% ( 5%) to clkin: single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 43 fig. 43 interrupt input timing fig. 44 standby timing px t w(portinl) t w(portinh) 69 70 [for input] px t w(portoutl) t w(portouth) 71 72 [for output] fig. 45 i/o port timing int sbi (input) (input) t w(int) t w(sbi) *1 63 64 *1 *1 the int and sbi signals can be input asynchronously. when returning from cpu sleep mode, the same timing applies. this timing value is "a value necessary for sampling the input to pins", however, not "a value that guarantees the interrupt acceptance". the interrupt request is a level-sensed input , and should be kept "l" until it is accepted. *2 the stby goes to an "l" level when switched to the standby mode. *3 when returning from standby mode, the stby signal goes to an "h" level 1 clkin after sampling that wkup has returned from "l" to "h", or 3 clkins after sampling that rst = "l". t d(clkin-stbyl) stby (output) 66 clkin (input) t d(clkin-stbyh) 68 *1 *2 *1 *3 degree phase of clkin. t d(clkin-stbyhx) 65 t d(clkin-stbylx) 67 internal clock (80 mhz) *1 the stby signal is synchronized with the internal clock therefore, its timing changes at 0, 90, 180 and 270 notes regarding these materials ? these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product b est suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. ? mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, origina ting in the use of any product data, diagrams, charts or circuit application examples contained in these materials. ? all information contained in these materials, including product data, diagrams and charts, represent information on products a t the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers co ntact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. ? mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used und er circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a pro duct contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ? the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these m aterials. ? if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licen se from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. ? please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detai ls on these materials or the products contained therein. keep safety first in your circuit designs! ? mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making y our circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. ? 1998 mitsubishi electric corp. first edition, effective september. 1998 specifications subject to change without notice. single-chip 32-bit cmos microcomputer mitsubishi microcomputers M32000D4BFP-80 package outline |
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